1. Field of the Invention
The present invention relates to a switch semiconductor circuit which performs switching of high-frequency signals, particularly to a switch semiconductor circuit with improved operation characteristics.
2. Description of the Related Art
In portable telephones, mobile wireless communication devices and the like which deal with high-frequency signals, there is used a switch semiconductor integrated circuit which makes use of a MESFET (Metal Semiconductor Field Effect Transistor) which is a field effect transistor made of a GaAs compound semiconductor, an HEMT (High Electron Mobility Transistor) or the like for performing switching of the high-frequency signals.
Because such a portable terminal apparatus of mobile wireless is driven by a battery, there is a need for a switch semiconductor integrated circuit capable of switching the high-frequency signals particularly at a low voltage. As such a switch semiconductor integrated circuit, an SPDT (Single Pole Dual Throw) switch circuit, for example, is publicly and widely known which is designed to include an inverter circuit for performing switching with one control signal (see, for example, Japanese Unexamined Patent Publication No. 164772/2002, p. 4, FIG. 1).
FIG. 7 shows one example of such a conventional SPDT switch circuit. Hereafter, this conventional circuit will be described with reference to FIG. 7.
Referring to FIG. 7, P1, P2, and P3 denote signal terminals; Q1, Q2, Q3, Q4, and Q5 denote FETs; S1 denotes a control bias application terminal; R1, R2, R3, R4, R5, and R6 denote resistors; C1, C2, and C3 denote depletion capacitors for shutting off a DC current; and V1 denotes a power source for supplying a driving voltage Vdd.
The inverter circuit in the exemplified circuit of FIG. 7 is a generally well-known DCFL (Direct Coupling FET Logic), where FETs of enhancement type are used as Q3, Q4, and Q5 constituting the inverter circuit, and FETs of depletion type are usually used as Q1 and Q2 for switching for the purpose of reducing the passage loss at the time of on-state.
In such an arrangement, when a high level voltage is applied to, for example, control bias application terminal S1, FET Q3 is turned into an on-state, whereby the gate of switch FET Q1 is set at the GND voltage. Also, because the other FET Q4 connected to control bias application terminal S1 is turned into the on-state, the gate of FET Q5 is set at the GND voltage as well. In result, FET Q5 of enhancement type is brought into an off-state, whereby power source voltage Vdd is applied from power source V1 to the gate of switch FET Q2 via load resistor R6. Further, the drain and source of switch FETs Q1, Q2 are set at the power source voltage Vdd via resistor R3.
Because such a voltage is supplied to the switch circuit, the voltage differences between the gate and drain and between the gate and source of switch FET Q2 will be zero, thereby making the drain and source of switch FET Q2 electrically connected with each other. On the other hand, power source voltage Vdd is applied between the gate and drain and between the gate and source of switch FET Q1 in a reverse direction in a Schottky junction, thereby making the drain and source of switch FET Q1 electrically non-conductive with each other. In result, signal terminal P1 and signal terminal P3 are electrically connected to enable passage of high-frequency signals, whereas signal terminal P1 and signal terminal P2 are electrically separated with each other.
On the other hand, when a voltage of low level is applied to control bias application terminal S1, the gate voltage of switch FET Q1 is set at Vdd, and the gate voltage of switch FET Q2 is set at GND voltage, whereby signal terminal P1 and signal terminal P2 are electrically connected with each other to enable passage of high-frequency signals, whereas signal terminal P1 and signal terminal P3 are electrically separated from each other, in contrast to the aforementioned case in which the high level voltage is applied to control bias application terminal S1.
In such a switch semiconductor integrated circuit, the maximum power that the switch semiconductor integrated circuit can handle is determined usually by the FET in the off-state. For example, it is publicly and widely known that the maximum power Pmax of high-frequency signals is given generally by the following formula (see, for example, “Monolithic Microwave Integrated Circuit (MMIC)”, Masayoshi AIKAWA and four others, Electronic Information Communication Society (a corporate juridical person), Jan. 25, 1997).Pmax=2{n(Vbias−Vp)}2/Z0 
Here, n denotes the number of switch FETs connected in series; Vp denotes the pinch-off voltage of the switch FET; Vbias denotes the bias voltage applied to the gate terminal of the switch FET of off-state; and Z0 denotes the characteristic impedance of the system. According to this formula, it will be understood that, in order to increase the maximum power Pmax in a switch semiconductor integrated circuit, the number of switch FETs connected in series might be increased, or the pinch-off voltage of the switch FET might be made shallow, or further the bias voltage might be raised.
However, a conventional switch semiconductor integrated circuit described above, which is used in a portable terminal apparatus, raises a problem in that the increase of the number of switch FETs invites an increase in the chip area, leading an increase in cost. Further, if the pinch-off voltage of the switch FET is made shallow, the increase of on-resistance of the switch FET is invited, thereby raising the problem of degradation of passage loss, which is one of the most important characteristics when the switch FET is turned into an on-state. Further, in a switch semiconductor integrated circuit used in a portable terminal apparatus, there is a problem in that the bias voltage of the switch FET cannot be simply raised as a result of the aforementioned demand for driving at a low voltage.
Therefore, as a means for increasing the bias voltage of an FET, there is proposed, for example, a technique as disclosed in Japanese Unexamined Patent Publication No. 112314/1999. Namely, according to this method, a DC voltage is generated from a high-frequency signal with the use of a DC voltage generating circuit composed of diodes, resistors, and capacitors, and a switch control voltage is generated from the higher one of the driving voltage and the DC voltage in accordance with the timing of switching the high-frequency signal, so as to raise the bias voltage.
However, according to this technique, the complex arrangement of the circuit raises the problem of inviting the increase of chip area and the cost increase due to increase in the number of components.